`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yu Zihao
// 
// Create Date: 2021/08/01 16:06:39
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: vivado 2019.1
// Description: 
// 
//    Value on ALUop input  |  Operation
//           00             |  Ain + Bin
//           01             |  Ain - Bin
//           10             |  Ain & Bin
//           11             |    ~Bin
// Dependencies: 
// 
// Revision: V1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ALU(Ain,Bin,ALUop,out,Z);
input [15:0] Ain, Bin;
input [1:0] ALUop;
output [15:0] out;
output Z;

reg [15:0] out;
reg stateZ;

 always @(*)begin
    case(ALUop)
        2'b00: out = Ain + Bin;
        2'b01: out = Ain - Bin;
        2'b10: out = Ain & Bin;
        2'b11: out = ~Bin;
        default: out = 16'b0;
    endcase
 end

 assign Z = ~(out ? 1'b1 : 1'b0);
 
endmodule
